High Throughput VLSI Architecture for Multiresolution Motion Estimation in High Definition AVS Video Encoder

This paper proposes a hardware friendly multiresolution motion estimation algorithm and VLSI architecture for high definition MPEG-like video encoder hardware implementation. By parallel searching and utilizing the high correlation in multiresolition reference pixels, huge throughput and computation in motion estimation due to large search window are alleviated considerably. Sixteen way parallel process element arrays with configurable multiplying technologies achieve fast search with regular data access and efficient data reuse. Also, the parallel arrays can be efficiently reused at three hierarchical levels for sequential motion vector refinement. The modified algorithm achieves a good balance between complexity and performance. Also, the logic circuit and on-chip SRAM consumption in the VLSI architecture are moderate.